Journal
PROCEEDINGS OF THE IEEE
Volume 98, Issue 12, Pages 2005-2014Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JPROC.2010.2066531
Keywords
Adiabatic switching; ferroelectric devices; low power; low-voltage logic devices; magnetic logic devices; negative capacitance; spin-FET; tunnel-FET
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Reduced power dissipation relative to the field-effect transistor (FET) is a key attribute that should be possessed by any device that has a chance of supplanting the FET as the ubiquitous building block for complex digital logic. We outline the possible physical approaches to achieving this attribute, and illustrate these approaches by citing current exploratory device research. We assess the value of the key exploratory research objectives of the semiconductor industry-sponsored Nanoelectronics Research Initiative (NRI) in the light of this pressing need to reduce dissipation in future digital logic devices.
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