Journal
PROCEEDINGS OF THE IEEE
Volume 97, Issue 1, Pages 31-42Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JPROC.2008.2007460
Keywords
Package-in-package; package-on-package; semiconductor device packaging; three-dimensional packaging
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The need to integrate more device technology in a given board space for handheld applications such as mobile phones has driven the adoption of innovative packages which stack such devices in the vertical or third dimension (3-D). Stacking of device chips in small and thin fine-pitch ball grid array packages has evolved into the stacking of packages themselves to achieve the same end. The advantage of stacking packages rather than device chips is that packages can be fully tested good prior to stacking. There are two primary ways to stack packages to achieve such vertical integration: package-on-package (PoP) and package-in-package (PiP). innovative variations of PoP and PiP are being developed to address specific packaging needs and market trends. This paper will detail some of the key technology supporting PoP and PiP packages currently in production and the development of new variations of such packages to address future trends.
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