Journal
PROCEEDINGS OF THE IEEE
Volume 96, Issue 2, Pages 343-365Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JPROC.2007.911072
Keywords
clock distribution; complementary metal-oxide-semiconductor (CMOS); device scaling; digital circuits; lithography; logic; manufacturability; memory; optimization; power distribution; regular circuit fabrics; statistical variability; yield
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Well-designed circuits are one key insulating layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to hide more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the Subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. we survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.
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