4.4 Article

Planar transformers for column parallel CCD clock drive

Publisher

ELSEVIER SCIENCE BV
DOI: 10.1016/j.nima.2009.07.103

Keywords

Column parallel CCD; Planar transformer; Substrate bounce

Funding

  1. Science and Technology Facilities Council [ST/G008280/1] Funding Source: researchfish
  2. STFC [ST/G008280/1] Funding Source: UKRI

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The LCFI Collaboration is developing the sensors, readout electronics and mechanical support structures for the Vertex Detector (VXD) of the International Linear Collider (ILC). High-speed readout is needed to ensure that the occupancy due to the pair production background at the ILC is kept below 1% level. In order to satisfy this requirement, Column Parallel CCDs (CPCCDs) and Column Parallel Readout chips (CPRs) have been developed. The CPCCD has to operate at a clock frequency of 50 MHz, which represents a difficult technical challenge due to the relatively large sensor capacitance. The design and performance of planar transformers, which can be used to provide the required 20 A clock current, are described. (C) 2009 Elsevier B.V. All rights reserved.

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