Numerical analysis of degradation kinetics in CdTe thin films

A time-dependent approach is introduced to numerically analyze the degradation of CdS/CdTe thin film photovoltaics under different stress conditions using the SCAPS-1D program. Under the stress conditions of light, temperature or bias, the excess charge carriers (holes/electrons) are created/accumulated within the CdTe layer which leads to a defect generation/increment mostly at the interface. The defect increment specially around the midgap level leads to the degradation of device parameters. Since the excess charge carriers and defect increment are coupled we examine several carrier kinetics such as the linear n- or p-model, bilinear np-model and quadratic n(2)-model. This comprehensive simulation is consistent with the polycrystalline nature of CdTe materials and their ambiguous degradation mechanism. Simulations are performed for short-circuited and open-circuited devices that are assumed to be also under stress conditions of temperature, dark and light. The degradation rate in the device parameters, variations in band diagrams and current voltage characteristics are analyzed and compared with the relevant experimental reports in literature. As a novelty, our analyses indicate that the degradation rate caused by the linear kinetics of the holes competes with the nonlinear kinetics of the electrons. Thus, holes can lead to a stronger degradation than that of electrons because of their smaller mobility in CdTe materials. Dividing the CdTe layer into several thinner sublayers in the SCAPS platform allows us to analyze the effect of the defect increment position on the device degradation. It is shown that the junction is critically sensitive to defects and charge carrier accumulation. These simulations reveal that the location of carrier/defect accumulation can be just as important as the carrier type and concentration. This simulation approach can be extended to other thin film materials, dye cells and perovskite materials and also to photodetectors and CMOS devices. (C) 2015 Elsevier Ltd. All rights reserved.