Journal
NANO LETTERS
Volume 12, Issue 7, Pages 3592-3595Publisher
AMER CHEMICAL SOC
DOI: 10.1021/nl301254z
Keywords
III-V CMOS; InAs; InGaSb; two-dimensional semiconductors; logic gate
Categories
Funding
- FCRP/MSD
- NSF COINS
- Intel
- NSF E3S Center
- Office of Science, Office of Basic Energy Sciences, Materials Sciences and Engineering Division, of the U.S. Department of Energy [DE-AC02-05CH11231]
- AFOSR [FA9550-10-1-0113]
- World Class University program at Sunchon National University
- National Research Foundation of Korea [R31-2012-000-10022-0] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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One of the major challenges in further advancement of RI V electronics is to integrate high mobility complementary transistors on the same substrate. The difficulty is due to the large lattice mismatch of the optimal p- and n-type III-V semiconductors. In this work, we employ a two-step epitaxial layer transfer process for the heterogeneous assembly of ultrathin membranes of III-V compound semiconductors on Si/SiO2 substrates. In this III-V-on-insulator (XOI) concept, ultrathin-body InAs (thickness, 13 nm) and InGaSb (thickness, 7 nm) layers are used for enhancement-mode n- and p- MOSFETs, respectively. The peak effective mobilities of the complementary devices are similar to 1190 and similar to 370 cm(2)/(V s) for electrons and holes, respectively, both of which are higher than the state-of-the-art Si MOSFETs. We demonstrate the first proof-of-concept III-V CMOS logic operation by fabricating NOT and NAND gates, highlighting the utility of the XOI platform.
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