4.8 Article

Low Operating Bias and Matched Input-Output Characteristics in Graphene Logic Inverters

Journal

NANO LETTERS
Volume 10, Issue 7, Pages 2357-2362

Publisher

AMER CHEMICAL SOC
DOI: 10.1021/nl100031x

Keywords

Graphene; alumina dielectric; logic gate; inverter; nanoelectronics

Funding

  1. Ministry of Education, Culture, Sports, Science and Technology of Japan [17069004, 21241038]

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We developed a simple and novel method to fabricate complementary-like logic inverters based on ambipolar graphene held-effect transistors (FETs) We found that the top gate stacks (with both the metal and oxide layers) can be simply prepared with only one-step deposition process and show high capacitive efficiency By employing such a top gate as the operating terminal, the operating bias can be lowered within 2 V In addition, the complementary p- and n-type FET pairs can be also simply fulfilled through potential superposition effect from the drain bias The inverters can be operated. with up to 4-7 voltage gains, in both the first and third quadrants due to the ambipolarity of graphene FETs For the first time, a match between the input and output voltages is achieved in graphene logic devices, indicating the potential in direct cascading of multiple devices for future nanoelectronic applications

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