4.6 Article

Surface Defects and Passivation of Ge and III-V Interfaces

Journal

MRS BULLETIN
Volume 34, Issue 7, Pages 504-513

Publisher

CAMBRIDGE UNIV PRESS
DOI: 10.1557/mrs2009.138

Keywords

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Funding

  1. IMEC Industrial Affiliation Program on Ge and III-V devices
  2. NSF-DMR
  3. Intel Corporation
  4. [IST-ET4US-2048]
  5. [SRC-NCRC-1437.003]
  6. [FCRP-MSD-887.011]

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The need for high-kappa gate dielectrics and metal gates in advanced integrated circuits has reopened the door to Ge and III-V compounds as potential replacements for silicon channels, offering the possibility to further increase the performances of complementary metal oxide semiconductor (CMOS) circuits, as well as adding new functionalities. Yet, a fundamental issue related to high-mobility channels in CMOS circuits is the electrical passivation of their interfaces (i.e., achieving a low density of interface defects) approaching state-of-the-art Si-based devices. Here we discuss promising approaches for the passivation of Ge and III-V compounds and highlight insights obtained by combining experimental characterization techniques with first-principles simulations.

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