Journal
MICROELECTRONIC ENGINEERING
Volume 109, Issue -, Pages 364-369Publisher
ELSEVIER
DOI: 10.1016/j.mee.2013.03.021
Keywords
High-K; Grain boundary; Dielectric Breakdown; Conductive-AFM
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Funding
- Singapore University of Technology and Design (SUTD) [SRG ASPE 2010 004]
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Grain boundaries (GBs) in polycrystalline high-kappa (HK) dielectric films affect the performance and reliability metrics of HK based advanced metal-oxide-semiconductor (MOS) devices. A full understanding of device reliability can only be had with the knowledge of the detrimental role of GB in degradation and breakdown (BD) of polycrystalline HK/interfacial layer (IL) dielectric stacks. In this work, we present a nanoscale resolution study on how the polycrystalline microstructure affects the degradation and BD at GB sites of polycrystalline HfO2 in HfO2/SiOx (x <= 2) dielectric stacks using conductive-atomic force microscopy (C-AFM), supported by a statistical failure distribution model and device level simulations. Results clearly show an enhanced trap generation and faster degradation of polycrystalline HfO2 gate dielectrics at GB sites as compared to the bulk (grain) regions implying shorter time-dependent dielectric breakdown (TDDB) lifetime at the GB sites. The SiOx IL below the degraded GB experiences a BD event when an enhanced electric field across the SiOx IL reaches the critical BD field, eventually triggering the overall BD of the HfO2/SiOx dielectric stack. (C) 2013 Elsevier B.V. All rights reserved.
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