Journal
MICROELECTRONIC ENGINEERING
Volume 86, Issue 3, Pages 287-290Publisher
ELSEVIER SCIENCE BV
DOI: 10.1016/j.mee.2008.09.024
Keywords
High-kappa; Breakdown; Stress-induced leakage current; Constant voltage stress; Time dependent dielectric breakdown
Ask authors/readers for more resources
A new smart algorithm with adaptive testing is developed for automatically monitoring gate dielectric degradation during CVS using SILC. In this approach, stress current is monitored with a sampling rate as fast as similar to 2 ms/point while SILC data are collected based on stress current changes and/or time intervals. This automated test was applied to study degradation of nMOS transistors with TiN/HfO(2) gate stacks where changes in the SILC data correlate directly with transitions in the stress current. From this SILC data, the differential resistance can be extracted and used to monitor conductivity throughout the degradation phase until breakdown. (C) 2008 Elsevier B.V. All rights reserved.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available