Design and performance analysis of a nanoscaled inverter based on wrap-around-gate nanowire MOSFETs

The design and analysis of a silicon nanowire inverter with a wrap-around-gate nMOS is presented and its performance is compared with that of a conventional inverter. The analysis shows that the nano-channel structure design can improve carrier mobility by suppressing the transverse component of the electric field. This results in an enhancement in the current drive of the nMOS, and contributes to lowering power consumption and the switching delay. Simulated power consumption and rise time of the proposed design was found to be about 20 mu W and 0.5 ns, respectively, compared with 2.5 mW and 1.5 ns achievable with conventional planar MOSFETs. Investigation of the gate length shows that a nMOS with shorter gates have an improved switching response compared with long channel devices.