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Operation and Modeling of Semiconductor Spintronics Computing Devices

Journal

JOURNAL OF SUPERCONDUCTIVITY AND NOVEL MAGNETISM
Volume 21, Issue 8, Pages 479-493

Publisher

SPRINGER
DOI: 10.1007/s10948-008-0343-y

Keywords

Logic devices; Computing; Transistor; CMOS; Spintronics; Spin FET; Gain; Ferromagnetic semiconductor; Semiconductor Bloch equations; Scaling; Quantum limit; Power dissipation

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Semiconductor spintronic devices are considered from the point of view of suitability for digital logic. Functionality of earlier proposed devices is reviewed for cascadability and signal gain. Spin gain transistor, which uses electronic control of ferromagnetism in semiconductors, is treated in more detail via semiconductor Bloch equations for both localized and free-carrier magnetic moments. Dependence of the steady state magnetization and temporal switching characteristics on material parameters is determined. Finally, fundamental physical limits for spintronic devices are determined via use of an idealized model. They are compared with similar limits for electronic devices. It is found that, though spintronic devices switch slower, their switching energy is smaller, therefore they scale with size on a curve with lower power dissipation.

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