Journal
JOURNAL OF PHYSICS D-APPLIED PHYSICS
Volume 47, Issue 20, Pages -Publisher
IOP PUBLISHING LTD
DOI: 10.1088/0022-3727/47/20/205102
Keywords
resistive switching memories; progressive reset; simulation of RRAMs; reset voltage extraction procedures
Categories
Funding
- Junta de Andalucia [P08-TIC-3580]
- Spanish Ministry of Science and Technology [TEC2012-32305, TEC2011-28660]
- EU under the FEDER program
- DURSI of the Generalitat de Catalunya [2009SGR78]
- ICREA ACADEMIA award
- NSFC [61322408, 61221004, 61274091]
Ask authors/readers for more resources
Reset processes in resistive random-access memory devices have been studied in depth. In particular, progressive transitions, where no clear current reduction steps are seen, are analysed by using a previously developed simulator and by comparing with experimental data of devices based on HfO2 oxides. It has been reported that the characterization of progressive reset processes can be performed by separately considering devices with a single conductive filament or devices with more than one conductive filament. In addition, making use of the experimental measurements shown, different numerical methods are proposed to extract the reset voltage. These methods are applied to different I-V reset curves and discussed.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available