Thermal characterization of vertical silicon nanowires

Arrays of vertically aligned silicon wires of 250 nm-4 mu m in diameter were fabricated in a top-down process using photolithography and deep reactive ion etching at cryogenic temperatures. Using the 3-omega method, thermal conductance of vertical silicon nanowires, i.e., nanopillars, was measured immediately on-chip without the need of breaking off single wires and mounting them into a special testing device. The Seebeck coefficient was measured with 2-mm(2) arrays of pillars of 260 nm in diameter, which were pressure-joined with bulk chips for testing. Testing was performed in the temperature range between 50 and 470 degrees C at applied temperature gradients of up to 190 degrees C. We found a reduction of the thermal conductivity to less than 30% of the bulk silicon, confirming that arrayed vertical nanowires fabricated in an economical top-down process can strongly promote silicon as a thermoelectric material.