Journal
JOURNAL OF INSTRUMENTATION
Volume 9, Issue -, Pages -Publisher
IOP PUBLISHING LTD
DOI: 10.1088/1748-0221/9/01/C01060
Keywords
VLSI circuits; Analogue electronic circuits; Front-end electronics for detector readout
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The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3 ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than +/- 0.9 LSB and integral-non-linearity (INL) of better than +/- 1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology.
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