Related references
Note: Only part of the references are listed.LSI implementation of a low-power 4 x 4-bit array two-phase clocked adiabatic static CMOS logic multiplier
Nazrul Anuar Nayan et al.
MICROELECTRONICS JOURNAL (2012)
Practical Strategies for Power-Efficient Computing Technologies
Leland Chang et al.
PROCEEDINGS OF THE IEEE (2010)
The Combinational and Sequential Adiabatic Circuit Design and Its Applications
Sompong Wisetphanichkij et al.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING (2009)
Energy-efficient GHz-class charge-recovery logic
Visvesh S. Sathe et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2007)
Charge-recovery computing on silicon
S Kim et al.
IEEE TRANSACTIONS ON COMPUTERS (2005)
Ultralow-power adiabatic circuit semi-custom design
A Blotti et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2004)
Ultra-low-power DLMS adaptive filter for hearing aid applications
CHI Kim et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2003)
NAND/NOR adiabatic gates: Power consumption evaluation and comparison versus the fan-in
M Alioto et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2002)
A comparison of some circuit schemes for semi-reversible adiabatic logic
A Blotti et al.
INTERNATIONAL JOURNAL OF ELECTRONICS (2002)
Power estimation in adiabatic circuits: A simple and accurate model
M Alioto et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2001)
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
D Maksimovic et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2000)