Diameter dependent performance of high-speed, low-power InAs nanowire field-effect transistors

The diameter dependent performance metrics of InAs nanowire (NW) field-effect transistors (FETs) are investigated using an analytical two-band model and a semiclassical ballistic transport model. The first analysis of the diameter dependence of the current, the gate delay time, the power-delay product, and the energy-delay product of InAs NW FETs, which operate in the quantum capacitance limit (QCL), are presented. Because of its small density of states, which results from the lower electron effective mass, relatively large diameter (<= 60 nm) InAs NW FETs operate in the QCL. Both the energy-delay and power-delay products are reduced as the diameter is reduced, and optimum designs are obtained for diameters in the range 10-40 nm. Power-delay product varies from 2x10(-20) to 63x10(-20) J for all devices with a source Fermi level range 0.1-0.2 eV. The gate delay time for all devices varies from 4 to 16 fs and decreases as the NW diameter increases. Analytical expressions are derived for the key device metrics for a single-moded device and compared with the numerical results. The NW FETs provide both ultralow-power switching and high speed.