Journal
NANOSCALE
Volume 7, Issue 17, Pages 8076-8083Publisher
ROYAL SOC CHEMISTRY
DOI: 10.1039/c5nr01126d
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Funding
- Fondazione Cariplo [2011-0373]
- EU FP7 Graphene Flagship [604391]
- PRIN project GRAF
- United States National Science Foundation (NSF)
- Air Force Office of Scientific Research (AFOSR)
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The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 mu m gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.
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