Journal
NANO LETTERS
Volume 15, Issue 12, Pages 8056-8061Publisher
AMER CHEMICAL SOC
DOI: 10.1021/acs.nanolett.5b03460
Keywords
silicon nanowire (SiNW); gate-all-around (GAA); vertical integration; field-effect transistor (FET); three-dimensional nonvolatile memory; one-route all-dry etch
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Funding
- Center for Integrated Smart Sensors - Ministry of Science, ICT & Future Planning as Global Frontier Project [CISS-2011-0031848]
- Pioneer Research Center Program through the National Research Foundation of Korea - the Ministry of Science, ICT & Future Planning [2012-0009594]
- Open Innovation Lab Project from the National Nanofab Center (NNFC)
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A vertically integrated multiple channel-based field-effect transistor (PET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.
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