Journal
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Volume 43, Issue 6, Pages 822-828Publisher
WILEY
DOI: 10.1002/cta.1981
Keywords
I; O circuit; voltage stress; bidirectional I; O; CMOS
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Funding
- National Research Foundation of Korea (NRF) - Korean Government (MSIP) [2013R1A2A2A01004958]
- MSIP (Ministry of Science, ICT & Future Planning), Korea, under the ITRC (Information Technology Research Center) support program [NIPA-2013-H0301-13-1013]
- Ministry of Public Safety & Security (MPSS), Republic of Korea [H8501-15-1010] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
- National Research Foundation of Korea [2013R1A2A2A01004958] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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A 5.25-V-tolerant bidirectional I/O circuit has been developed in a 28-nm standard complementary metal-oxide-semiconductor (CMOS) process with only 0.9 and 1.8V transistors. The transistors of the I/O circuit are protected from over-voltage stress by cascode transistors whose gate bias level is adaptively controlled according to the voltage level of the I/O pad. The n-well bias level of the p-type metal-oxide-semiconductor transistors of the I/O circuit is also adapted to the voltage level of the I/O pad to prevent any junction leakage. The 5.25-V-tolerant bidirectional I/O circuit occupies 40 mu mx170 mu m of silicon area. Copyright (c) 2014 John Wiley & Sons, Ltd.
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