Journal
IET IMAGE PROCESSING
Volume 8, Issue 1, Pages 33-43Publisher
INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/iet-ipr.2012.0586
Keywords
cryptography; field programmable gate arrays; image colour analysis; Xilinx Virtex 4 FPGA; bit permutations; XORing; chaotic sequence; colour image encryption; controllable chaos generator; hardware stream cipher
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This study presents hardware realisation of chaos-based stream cipher utilised for image encryption applications. A third-order chaotic system with signum non-linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s.
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