Journal
IEICE TRANSACTIONS ON ELECTRONICS
Volume E94C, Issue 7, Pages 1206-1211Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
DOI: 10.1587/transele.E94.C.1206
Keywords
sensor node; power management; power switch; energy harvesting; CMOS
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The design and performance of a sub-nanoampere two-stage power management circuit that uses off-chip capacitors for energy accumulation are presented. Focusing on the leakage current and the transition time of the power switch transistor, we estimated the minimum current for accumulating. On the basis of the results, we devised a two-stage power management architecture for sub-nanoampere operation. The simulated and experimental results for the power management circuit describe the accumulating operation with a 1-nA current source.
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