Journal
IEICE ELECTRONICS EXPRESS
Volume 10, Issue 23, Pages -Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
DOI: 10.1587/elex.10.20130772
Keywords
field-programmable gate array; magnetic tunnel junction device; nonvolatile logic-in-memory architecture; power-gating
Categories
Funding
- Japan Society for the Promotion of Science (JSPS)
- Council for Science and Technology Policy (CSTP)
- VLSI Design and Education Center (VDEC), the University of Tokyo
- Cadence, Inc.
Ask authors/readers for more resources
A nonvolatile field-programmable gate array (NVFPGA) test chip with 240 tiles (the basic components) in a 12 x 20 2D-array is fabricated by 90 nm CMOS and 70 nm magnetic tunnel junction (MTJ) technologies. Since not only circuit configuration data but also temporal data are still remained in the MTJ devices even when the power supply is cut off, standby power dissipation is completely eliminated by utilizing tile-level power gating. Power reduction is further accelerated by skipping wasted write operations of nonvolatile flip-flops (NVFFs) for storing temporal data when the temporal data and the stored one are the same. As a typical application, a motion-vector prediction function is implemented on the proposed NVFPGA, which results in a write power reduction of 77% compared to that of a conventional MTJ-based NVFPGA and a total power reduction of 70% compared to that of an SRAM-based FPGA.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available