Journal
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume 19, Issue 4, Pages 548-558Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2009.2038389
Keywords
CODEC; crosstalk avoidance codes (CACs); interconnect; numeral systems; on-chip bus
Funding
- Thales Communications Inc.
- Commonwealth of Pennsylvania, Department of Community and Economic Development, through the Pennsylvania Infrastructure Technology Alliance (PITA)
- Directorate For Engineering
- Div Of Electrical, Commun & Cyber Sys [0925890] Funding Source: National Science Foundation
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Low-complexity CODECs for two classes of crosstalk avoidance codes (CACs), forbidden pattern codes (FPCs) and forbidden transition codes (FTCs), have been recently proposed based on Fibonacci-based binary numeral system. In this paper, we first generalize this idea and establish a generic framework for the CODEC design of all classes of CACs based on binary mixed-radix numeral systems. Using this framework, we then propose novel CODEC designs for three important classes of CACs, one lambda codes (OLCs), FPCs, and forbidden overlapping codes (FOCs). Our CODEC designs have area complexity and delay that increase quadratically with the size of the bus, while achieving optimal or nearly optimal code rates. Our CODECs also have simple and regular circuitry, and can easily achieve very high throughput by pipelining. Our efficient CODECs, used with such techniques as partial coding, help to make CACs a practical option in combating crosstalk delay, which is a bottleneck in deep submicrometer system-on-chip designs.
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