Journal
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume 19, Issue 11, Pages 2023-2032Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2010.2063444
Keywords
CMOS-nano hybrid circuit; field-programmable gate array (FPGA); nanojunction; resistive RAM (RRAM); 3-D integration
Funding
- Semiconductor Research Corporation
- National Science Foundation
- Air Force Small Business Technology Transfer Program
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In this paper, a novel CMOS-nano hybrid reconfigurable field-prgrammable gate array architecture (rFPGA) is introduced based on resistive memory (RRAM) devices. Different from the existing crossbar-based CMOS-nano architectures, rFPGA consists of mainly 1T1R RRAM structures that can be fabricated by using a CMOS-compatible process. These devices can efficiently establish FPGA block memories. More importantly, novel RRAM routing switches are developed to replace the CMOS routing switches to achieve significant density enhancement and power reduction. The simulation results demonstrate that 2-D and 3-D rFPGAs provide at least 2x-3x overall improvement in terms of area with 20% lower power consumption, compared with the corresponding CMOS FPGAs.
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