Area Scaling for Backend Dielectric Breakdown

Backend dielectric breakdown is an increasingly important issue for advanced CMOS processes due to the use of progressively lower k dielectrics in the backend. This paper presents area-scaling formulas to enable full chip failure rate projection from test structure data. The area-scaling formulas are based on the negative binomial defect distribution, which in the limit is equivalent to models based on the Poisson distribution. Both the Weibull and log-normal distributions are considered for data characterization. The results are applied to data measured from backend comb structures, and reveals a low level of defect clustering.