Journal
IEEE TRANSACTIONS ON POWER ELECTRONICS
Volume 27, Issue 8, Pages 3467-3471Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2012.2190425
Keywords
DC offset error; integral operation; phase-locked loop (PLL); scaling error; single-phase grid-connected converter (SPGC); synchronous d-axis voltage
Categories
Funding
- National Science Foundation [1124658]
- National Research Foundation of Korea [과C6B1614] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
- Directorate For Engineering
- Div Of Electrical, Commun & Cyber Sys [1124658] Funding Source: National Science Foundation
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This letter proposes a dc offset error compensation algorithm for synchronous reference frame phase-locked loop (PLL) in single-phase grid-connected converters. The errors generated from the grid voltage measurement circuits can be divided into dc offset and scaling errors. These errors may cause the undesirable periodic ripples with grid frequency in the synchronous reference frame PLL. As a result, the performance of the power conversion systems is degraded. In this letter, the effects of the dc offset and scaling errors are comprehensively analyzed based on the synchronous dq frame PLL. In particular, the dc offset error can be estimated and compensated by controlling the synchronous d-axis voltage in a PLL system to be zero. The proposed algorithm does not require any additional hardware and can be implemented by a simple proportional-integral controller and an integral operation. Experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.
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