NEM Relay-Based Sequential Logic Circuits for Low-Power Design

Nanoelectromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behaves like an ideal switch. The zero leakage operation has generated lot of interest in low power logic design using these relays [1], [2]. This paper presents various sequential circuit topologies using NEM relays and analyzes their power, performance, and area tradeoffs. The mechanical delay is inversely proportional to the gate-base voltage V-gb. This paper also presents an integrated voltage doubler-based flip-flop that improves the performance by 2x by overdriving V-gb. An electromechanical model which accounts for the mechanical, electrical, and dispersion effects of the suspended gate relay operating at 1 V with a nominal air gap of 5-10 nm has been developed based on published fabrication results in [1]. Three sequential logic benchmark circuits were designed using NEM relays to verify the correctness of operation of the proposed circuits. This study explores different relay-based latch and flip-flop topologies, proposes fast sequential circuits that can operate at a frequency of 1/2t(m) (theoretical fastest frequency for NEM relay logic circuits) and further improves speed of sequential circuits by distributed charge boosting.