4.4 Article

One-Diode Model Equivalent Circuit Analysis for ZnO Nanorod-Based Dye-Sensitized Solar Cells: Effects of Annealing and Active Area

Journal

IEEE TRANSACTIONS ON NANOTECHNOLOGY
Volume 11, Issue 4, Pages 763-768

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNANO.2012.2196286

Keywords

Annealing; circuit analysis; equivalent circuits; photovoltaic cells; semiconductor defects

Funding

  1. Centre of Excellence in Nanotechnology, Asian Institute of Technology, National Nanotechnology Center
  2. National Science and Technology Development Agency
  3. Royal Thai Government

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Electrical characteristics of 1-D zinc oxide (ZnO) nanorod-based dye-sensitized solar cells (DSSCs) were experimentally measured and followed by theoretical analysis using simple one-diode model. Defect sites (mostly oxygen vacancies) in ZnO are typically responsible for lower DSSC performance, which are removed by annealing the ZnO nanorods at high temperatures up to 450 degrees C. The DSSC performances with respect to the different annealing temperatures (250 degrees C, 350 degrees C, and 450 degrees C) were determined by measuring their I-V characteristics at 1-sun irradiation (AM 1.5G). The variations in series and shunt resistances of DSSC were estimated by fitting the experimental I-V characteristics with the ideal I-V curve obtained from the one-diode equivalent model of the DSSC. By increasing annealing temperature, reduction in the series resistance R-s of the DSSCs with a subsequent increase in the shunt resistance R-sh was obtained. Annealing temperature of 350 degrees C was found to be optimum at which maximum DSSC performances with 1-cm(2) cell active area showing minimum R-s (0.02 k Omega) with high R-sh (1.08 k Omega) values were observed. Reduction in the active area of the DSSCs from 1 to 0.25 cm(2) and further to 0.1 cm(2) demonstrated improved device performance with similar to 56% and similar to 24% enhancement in the fill factor and open-circuit voltage V-oc, respectively, due to the reduced sheet resistance and lower recombination rate resulting low series resistance and high shunt resistance, respectively. At the optimum annealing temperature, maximum DSSC efficiency of 4.60% was obtained for the 0.1-cm(2) cell active area.

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