Journal
IEEE TRANSACTIONS ON NANOTECHNOLOGY
Volume 10, Issue 4, Pages 778-788Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNANO.2010.2079941
Keywords
Low power; nanomagnet; spintronics; systolic array architectures
Categories
Funding
- Nanoelectronics Research Initiative
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MOSFET scaling is facing overwhelming challenges with increased parameter variations, exponentially higher leakage current, and higher power density. Thus, researchers have started looking at alternative switching devices and spintronics-based computing paradigms. Nanomagnet-based computing is one such paradigm with intrinsic switching energy close to thermal limits and scalability down to 5 nm. In this paper, we explore the possibility of nanomagnet-based design using nonmajority gates. The design approach can offer significant area, delay, and energy advantages compared to majority-gate-based designs. Moreover, new clock technologies and architectures are developed to improve computation robustness and power dissipation of nanomagnet systems. We also developed a comprehensive device/circuit/system compatible simulation framework to evaluate the functionality and architecture of a nanomagnet system and conducted a feasibility/comparison study to determine the effectiveness of the technology compared to standard digital electronics. Performance results from a nanomagnet-based 16-point discrete cosine transform (DCT) with enhanced clock architecture, narrow gap cladding of nanomagnets, or embedding nanomagnets in solenoid with steel core, together with near neighbor system architecture, show up to 10ximprovement over subthreshold 15 nm CMOS (Vdd = 90 mV) design, using energy-delay(0.5)-area product (ED(0.5)A) as comparison metric. Finally, we explored the scalability of nanomagnets and the effectiveness of field-based switching.
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