Journal
IEEE TRANSACTIONS ON NANOTECHNOLOGY
Volume 9, Issue 6, Pages 675-678Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNANO.2010.2052108
Keywords
Low-power memristors; resistive memories; self-adjustment circuit; variation-tolerant memristors
Categories
Funding
- Kookmin University
- Nano IP/SoC Promotion Group of the Seoul [10560]
- SRC/ERC of MOST/KOSEF [R11-2005-048-00000-0]
- ETRI System Semiconductor Industry Promotion Center
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Memristive devices such as memristors that have been intensively studied for their possibilities as a strong candidate for future memories are known to have two problems. First, they need a large current in write operation, and second their process-V-DD-temperature (PVT) variations are large compared with the conventional DRAM and FLASH memories. Moreover, the large writing current can be magnified with PVT variations. In this letter, a new write circuit is proposed to prevent unnecessary power loss by using a self-adjusting circuit for properly sizing the writing pulsewidth, thereby minimizing power consumption. The simulation results show that self-adjusting the pulsewidth can save power by 76% on average, compared to the conventional write circuit with a fixed pulsewidth.
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