4.4 Article Proceedings Paper

High-performance twin silicon nanowire MOSFET (TSNWFET) on bulk Si wafer

Journal

IEEE TRANSACTIONS ON NANOTECHNOLOGY
Volume 7, Issue 2, Pages 181-184

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNANO.2008.917843

Keywords

bulk MOSFET; gate all around (GAA); high performance; MOSFET; nanowire; TSNWFET; twin silicon nanowire; 5 nm

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A gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on a bulk Si wafer is successfully fabricated to achieve extremely high-drive currents of 2.37 mA/mu m for n-channel and 1.30 mA/mu m for p-channel TSNWFETs with mid-gap TiN metal gate that are normalized by a nanowire diameter. It also shows good short-channel effects immunity down to 30-nm gate length due to the GAA structure and the nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.

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