Vertical topologies of miniature multispiral stacked inductors

Vertical topologies of on-chip silicon miniature multispiral stacked inductors are addressed, which have been fabricated by a 0.18-mu m CMOS process. A generalized topological circuit model is first developed with mutual capacitive and inductive couplings treated appropriately. A set of analytical equations is given for calculating all mutual frequency-independent (dc) inductances among different spirals. The partial-element equivalent-circuit method is implemented for capturing frequency- and temperature-dependent resistances and inductances (ac) of arbitrary spiral-stacked geometries by which mutual inductive coupling between different spirals are investigated. According to the fabricated four- to six-spiral stacked inductors and the measured two-port S-parameters, modeling and experimental studies are carried out so as to verify applicability and scalability of the proposed topological model. Excellent agreement between them are achieved in the characterization of inductances and Q factors of all samples beyond their self-resonant frequencies.