Journal
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
Volume 58, Issue 3, Pages 530-540Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIM.2008.2005080
Keywords
Field-programmable gate array (FPGA); time measurement circuit; time-to-digital converter (TDC); Vernier delay line (VDL)
Funding
- Natural Sciences and Engineering Research Council (NSERC) of Canada
- Regroupement Strategique en Microsystemes du Quebec
- IonWerks (Houston. TX)
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We present a multihit time-to-digital converter (TDC) architecture implemented in a field-programmable gate array (FPGA) with minimized timing overhead. The TDC circuit provides two-level fine-time interpolation. The fine interpolator is a matrix of Vernier delay cells interconnected in a topology to provide two propagation paths for the incoming data pulse. Two methods of calibration are presented to estimate the component delays. The TDC circuit achieves time measurements with a resolution of 75 ps with an average precision of similar to 300 ps and is capable of detecting incoming pulses at a distance of 7.5 ns or more from each other.
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