4.8 Article

Formal Methods for Systems Engineering Behavior Models

Journal

IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS
Volume 4, Issue 4, Pages 280-291

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TII.2008.2008998

Keywords

Embedded system design; formal verification; systems engineering; time Petri nets; timed bisimulation

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Safety analysis in systems engineering (SE) processes, as usually implemented, rarely relies on formal methods such as model checking since such techniques, however powerful and mature, are deemed too complex for efficient use. This paper thus aims at improving the verification practice in SE design: considering the widely-used model of enhanced function flow block diagrams (EFFBDs), it formally establishes its syntax and behavioral semantics. It also proposes a structural translation of EFFBDs to transition time Petri nets (TPNs); this translation is then proved to preserve the behavioral semantics (i.e., timed bisimilarity). After proving results on the boundedness of the resulting TPNs, it was possible to extend a number of fundamental properties (such as the decidability of liveness, state-access, etc.) from bounded TPNs to so-called bounded EFFBDs. Finally, these results led to both implementing and integrating a formal verification tool within a development platform for system design for defense applications and in which the underlying complexity is totally concealed from the end-user.

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