Performance Improvement of a Prefiltered Synchronous-Reference-Frame PLL by Using a PID-Type Loop Filter

Control Parameters design of a three-phase synchronous reference frame phase locked loop (SRF-PLL) with a prefiltering stage (acting as the sequence separator) is not a trivial task. The conventional way to deal with this problem is to neglect the interaction between the SRF-PLL and prefiltering stage, and treat them as two separate systems. This approach, although very simple, is not optimum as the prefiltering stage and the SRF-PLL may have comparable dynamics. The aim of this paper is to develop a systematic and efficient approach to design the control parameters of the SRF-PLL with prefiltering stage. To this end, the paper first optimizes the performance of the prefiltering stage in detection of the sequence components. The paper then proceeds to reduce the interaction between the prefiltering stage and SRF-PLL, which is achieved by employing a derivative-filtered proportional-integral-derivative controller as the loop filter (instead of the commonly adopted proportional-integral controller) and arranging a pole-zero cancellation. The suggested method is simple and efficient, and is applicable to the joint operation of different sequence separation techniques and the SRF-PLL. The effectiveness of the suggested design approach is confirmed through extensive experimental results.