Self-Aligned Process for Selectively Etched p-GaN-Gated AlGaN/GaN-on-Si HFETs

A process for an enhancement-mode p-GaN-gated heterostructure field-effect transistor with self-aligned structuring of the p-GaN is proposed. A gate-first process is employed, for which the gate metallization acts as contact and etch mask simultaneously. In the access region, the p-GaN is selectively removed in a dryetch process by a Cl-2/N-2/O-2 gas mixture. Due to self-aligned processing and precise etch depth control, devices achieve a high saturation current of 554 mA .mm(-1), a threshold voltage of 1.08 V, breakdown voltages up to 560 V, and dynamic R-ON, increase of 45% for 200-V stress bias.