Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 61, Issue 8, Pages 2820-2826Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2014.2327514
Keywords
Crossbar; resistive random access memory (RRAM); selector device; sneak path; write margin; write scheme
Funding
- Air Force Office of Scientific Research, Arlington, VA, USA, through Multidisciplinary University Research Initiative [FA9550-12-1-0038]
- National Science Foundation [ECCS-0954621]
- Ministry of Education, Science and Technology, National Research Foundation of Korea [2013R1A6A3A03061299]
- Directorate For Engineering [0954621] Funding Source: National Science Foundation
- Div Of Electrical, Commun & Cyber Sys [0954621] Funding Source: National Science Foundation
- National Research Foundation of Korea [2013R1A6A3A03061299] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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A comprehensive analysis of write operations (SET and RESET) in a resistance-change memory (resistive random access memory) crossbar array is carried out. Three types of resistive switching memory cells-nonlinear, rectifying-SET, and rectifying-RESET-are compared with each other in terms of voltage delivery, current delivery, and power consumption. Two different write schemes, V/2 and V/3, were considered, and the V/2 write scheme is preferred due to much lower power consumption. A simple numerical method was developed that simulates entire current flows and node voltages within a crossbar array and provides a quantitative tool for the accurate analysis of crossbar arrays and guidelines for developing reliable write operation.
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