Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 61, Issue 7, Pages 2287-2293Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2014.2323085
Keywords
Charge trapping; device modeling; high-kappa dielectric; positive bias temperature instability (PBTI)
Ask authors/readers for more resources
We propose a physical model for the fast component (<1 s) of the positive bias temperature instability (PBTI) process in SiOx/HfO2 gate-stacks. The model is based on the electron-phonon interaction governing the trapping/emission of injected electrons at the preexisting defects in the dielectric stack. The model successfully reproduces the experimental time dependences of the V-TH shift on both stress voltage and temperature. Simulations allow the extraction of the physical characteristics of the defects contributing to PBTI, which are found to match those assisting the leakage current in these stacks (i.e., oxygen vacancies).
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available