Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 60, Issue 11, Pages 3690-3695Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2013.2282000
Keywords
Conductive bridging; conductive-bridging random access memory; electrochemical memory cell (ECM); high-performance memory; low-power memory; thermal stability
Funding
- Interuniversity Microelectronics Centre's Industrial Affiliation program on RRAM
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In this paper, we optimize the stack of a 90-nm CMOS-friendly W\Al2O3\Cu conductive-bridging random access memory cell integrated in the one-transistor/one-resistor configuration. We show that the excellent Cu buffering properties of a TiW layer inserted at the Al2O3\Cu interface make it possible, on one hand, to ensure cell integrity after back-end-of-line processing at 400 degrees C and, on the other, to obtain excellent memory performances. After optimization of the Al2O3 layer thickness, the cell exhibits highly controlled set and reset operations, a large memory window, fast pulse programming (10 ns) at low voltage (<3 V), and low-current (10 mu A), and multilevel operation. Finally, 10(6) cycles of write endurance lifetime with up to a three-decade memory window is demonstrated, and state stability is assessed up to 125 degrees C.
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