Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 60, Issue 10, Pages 3197-3203Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2013.2278677
Keywords
Au-free; GaN on Si; gate dielectric; power semiconductor devices; semiconductor-insulator interfaces
Funding
- National Excellence Fellowship
- National Science Foundation [ECCS-1028910]
- Office of Naval Research [N00014-12-1-0971]
- Directorate For Engineering
- Div Of Electrical, Commun & Cyber Sys [1028910] Funding Source: National Science Foundation
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We report on the investigation of the charge trapping characteristics of dielectric-gated AlGaN/GaN high electron mobility transistors (HEMTs) with atomic layer deposited HfO2 (Tetrakis-(ethylmethylamino)hafnium and H2O precursors). The impact of process development and tool contamination in an Au-free 200-mm silicon CMOS line is discussed. The interfacial GaOxNy layer is proposed to be the primary location of long time constant traps. We examine the impact of these trap states on threshold voltage engineering of the gate stack. Enhancement mode operation of HEMTs is demonstrated, and the stability of enhancement mode is discussed.
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