Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications

We have experimentally studied the scaling behavior of sub-100-nm InAs high-electron mobility transistors (HEMTs) on InP substrate from the logic operation point of view. These devices have been designed for scalability and combine a thin InAlAs barrier and a thin channel containing a pure InAs sub-channel. InAs HEMTs with gate length down to 40 nm exhibit excellent logic figures of merit, such as I-ON/I-OFF = 9 x 10(4), drain-induced-barrier lowering = 80 mV/V, S = 70 mV/dec, and an estimated logic gate delay of 0.6 ps at V-DS = 0.5 V. In addition, we have obtained excellent high-frequency operation with L-g = 40 nm, such as f(T) = 491 GHz and f(max) = 402 GHz at V-DS = 0.5 V. In spite of the narrow bandgap of InAs subchannel, under the studied conditions, our devices are shown not to suffer from excessive band-to-band tunneling. When benchmarked against state-of-the-art Si devices, 40-nm InAs HEMTs exhibit I-ON = 0.6 A/mu m at I-Leak = 200 nA/mu m. This is about two times higher ION than state-of-the-art high-performance 65-nm nMOSFET with comparable physical gate length and I-Leak.