Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 56, Issue 11, Pages 2414-2422Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2009.2030635
Keywords
CMOS image sensor (CIS); column-parallel cyclic ADC; digital correlated double sampling (CDS); low random noise; low vertical fixed pattern noise (VFPN); single-ended ADC
Funding
- Knowledge Cluster Initiative of the Ministry of Education, Culture, Sports, Science and Technology
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A high-performance CMOS image sensor (CIS) with 13-b column-parallel single-ended cyclic ADCs is presented. The simplified single-ended circuits for the cyclic ADC are squeezed into a 5.6-mu m-pitch single-side column. The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB. An ultralow vertical fixed pattern noise of 0.1 e(rms)(-) is attained by a digital CDS technique, which performs A/D conversion twice in a horizontal scan period (6 mu s). The implemented CIS with 0.18-mu m technology operates at 390 frames/s and has 7.07-V/lx . s sensitivity, 61-mu V/ e(-) conversion gain, 4.9-e(rms)(-) read noise, and less than 0.4 LSB differential nonlinearity.
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