Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 55, Issue 1, Pages 163-174Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2007.911352
Keywords
CMOS digital integrated circuits; leakage currents; logic design; low-power electronics; matching; static random access memory (SRAM); subthreshold; yield estimation
Ask authors/readers for more resources
Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-V-t circuits, but are plagued by increased variation and reduced I-ON/I-OFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metries are presented.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available