Journal
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume 31, Issue 7, Pages 994-1007Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCAD.2012.2185930
Keywords
Analytical circuit model; MRAM; NAND Flash; nonvolatile memory; phase-change random-access memory (PCRAM); resistive random-access memory (ReRAM); spin-torque-transfer memory (STT-RAM)
Categories
Funding
- National Science Foundation [1147388, 0903432]
- DoE [DE-SC0005026]
- Semiconductor Research Corporation
- Division of Computing and Communication Foundations
- Direct For Computer & Info Scie & Enginr [1147388, 0903432] Funding Source: National Science Foundation
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Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density-optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.
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