Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 55, Issue 5, Pages 389-393Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2007.914891
Keywords
delta-sigma (Delta Sigma) analog-to-digital converter (ADC); MASH; power consumption
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This brief discusses the design tradeoffs for cascaded delta-sigma (Delta Sigma) analog-to-digital converters. Increasing the order of the first loop allows a tradeoff between aggressive noise shaping and moderate operational transconductance amplifier (OTA) specifications. A comparison between fourth-order topologies indicates that for a cascade 3-1 topology, 55-dB OTA gain is sufficient for 96-dB signal-to-noise-distortion ratio while 5% coefficient mismatch results in less than 4-dB degradation. Dependent on the ratio between the power consumption of the digital recombination and decimation filter and that of the analog loop filter, the optimal topology can be chosen. A cascade 3-1 converter is most efficient when this ratio lies between 0.54 and 0.97. A design in a 65-nm CMOS technology demonstrates the performance of a cascade 3-1 converter.
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