Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 66, Issue 1, Pages 215-225Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2018.2866932
Keywords
Racetrack memory; high density; ring-shaped; L2 cache
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Funding
- National Natural Science Foundation of China [61504006, 61571023]
- Young Elite Scientist Sponsorship Program by CAST [2017QNRC001]
- National Key Technology Program of China [2017ZX01032101]
- [B16001]
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Information storage and transfer via current-induced domain wall (DW) motions exhibit significant density-speed-energy advantages, which inspires numerous emerging devices and circuits, such as racetrack memory (RM). However, the hi-directional propagation of DWs in the conventional tape-shaped nanowire will lead to data overflow issue, implicitly deteriorating storage density and operational performances. In this paper, we propose a non-volatile cache design based on spin-orbit torque-driven ring-shaped RM. The systematical investigations, covering from device modeling, to circuits design, to hit-cell layout design, and to system evaluation have been carried out. Thanks to the cells-overlapping design, the proposed RM L2 cache can achieve 48x, 16x, and 8x improvements in term of capacity, compared with iso-area caches based on static random access memory (SRAM), spin transfer torque magnetic RAM (STT-MRAM), and tape-shaped RM, respectively. As proved by 4-core system experiment results, the proposed RM cache can improve 30.7% instructions per cycle (IPC) and save 58.2% energy compared with SRAM cache.
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