Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 61, Issue 8, Pages 2326-2336Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2014.2304656
Keywords
High integrated nonlinearity; redundancy and error correction; time-of-flight (ToF) application; time-to-digital converter (TDC); zoom-in architecture; 3-D Vernier space
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Funding
- National Research Foundation of Korea - Korea Government (MISP) [NRF-2013R1A2A2A05005818]
- IDEC Corporation
- National Research Foundation of Korea [2013R1A2A2A05005818] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13-mu m CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of +/- 1.5 LSB, a power consumption of 328.8 mu W, and a die area of 0.28 mm(2).
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