Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 56, Issue 7, Pages 1301-1312Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2008.2006642
Keywords
Adaptive equalizers; adaptive signal detection; analog-to-digital conversion; charge injection; EPROM; equalizers; flash ADC; floating gate; histogram equalization; learning systems; mixed analog-to-digital integrated circuits; nonlinear circuits; nonvolatile analog storage; Nyquist rate conversion; programmable circuits; quantization; training; tunable circuits and devices; tunneling; unsupervised learning
Categories
Funding
- National Science Foundation [0238061]
- Direct For Computer & Info Scie & Enginr
- Division of Computing and Communication Foundations [0238061] Funding Source: National Science Foundation
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A 6-b 750-MS/s flash analog-to-digital converter ( ADC) uses nonvolatile analog storage for reference levels and achieves a signal-to-noise-plus-distortion ratio (SNDR) and a spurious-free dynamic range of 37.2 and 48.6 dB, respectively. The architecture comprises an array of adaptive floating-gate comparators that enables storage and programming of reference levels, eliminating the need for resistive ladders. Reference levels may be programmed either manually by the user or autonomously during normal analog-to-digital conversion. Autonomous programming achieves histogram equalization by adjusting reference levels for finer resolution and greater sensitivity at frequently visited signal values. When programmed manually, the ADC achieves 34.3-dB SNDR at 750 MS/s for input frequencies up to 2.07X Nyquist rate, with a differential full-scale input range of 1 V. We observe integral nonlinearity and differential nonlinearity of less than 0.27 least significant bit at the Nyquist rate. One-month continuous operation shows no signs of reference-level drift due to charge leakage and maintains a constant bit error rate of 2.93 x 10(-9) sample.
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