4.4 Article

Improved Fabrication Yield for 10-V Programmable Josephson Voltage Standard Circuit Including 524288 NbN/TiN/NbN Josephson Junctions

Journal

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
Volume 20, Issue 2, Pages 71-75

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TASC.2010.2041349

Keywords

Cryocooler; double barrier; NbN; programmable Josephson voltage standard (PJVS); TiN

Funding

  1. New Energy and Industrial Technology Development Organization

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A 10-V programmable Josephson voltage standard (PJVS) circuit including 524 288 vertically stacked NbN/TiN/NbN Josephson junctions was successfully fabricated without any defects. The chip was cooled with a compact cryocooler at a temperature of 9.8 K and generated an output voltage of 17.3 V with the first Shapiro step height of 1.0 mA under microwave irradiation at 16 GHz. Furthermore, the circuit design having the high output voltage increased the number of available chips for the 10-V PJVS. The fabrication yield for the chip, which generates greater than 10 V, was 36%, which is ten times greater than that for a perfect chip without any defects. This method was not effective for the chip that had serious defects, such as a disconnection across the array or short between the array and ground; thus, efforts to reduce such defects, e. g., frequent maintenance inside vacuum chambers for film preparation and etching, were found to be essential.

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